1. Field of the Invention
The present invention relates to solid-state image sensors and, more particularly, to an interline-transfer CCD (Charge Coupled Device) image sensor for increasing horizontal resolution by varying the structure and array of photodiodes and vertical CCD channels to obtain higher resolution.
2. Background and Prior Art
The solid-state image sensors form images by transferring signals generated by light incident on photodiode cells to detection regions through the CCD.
Most of the presently used video processors utilize the interlaced scanning method. One frame of an image is made by both the first odd field scanning in sequence of 1, 3, 5, . . . , and the next even field scanning in sequence of 2, 4, 6, . . . The solid-state image sensors provide the sum signals of adjacent upper and lower photodiodes and these sum signals are combined in the odd and even fields.
Referring to two reports "Generation Mechanism and Elimination of Fixed Pattern Noise in Dual-Channel Horizontal-CCD Register Image Sensor", IEEE Transaction on Electron Devices, Vol. 35, No. 11, November, 1988 and "A 1/2-inch 410,000-pixel CCD Image Sensor with Feedback Field-Plate Amplifier", IEEE International Solid State Circuits Conference, pp. 208-209, 1991, the driving frequency of the horizontal CCD is increased as the solid-state image sensors achieve higher pixel density for higher resolution. It is, however, beyond the capacity of a CCD driver circuit and degrades the efficiency of charge transfer. Accordingly, a 2-stage horizontal CCD structure is employed in order to reduce the CCD driving frequency.
As seen in the above references higher pixel density is achieved by improvement of charge treatment, charge transfer and output amplifiers, but there still remain some problems since it has to be achieved within a predetermined chip area.
Also, even in the case of the 2-stage horizontal CCD structure case, fixed pattern noise is generated due to the characteristic difference between two horizontal CCD channels or between two output amplifiers.
FIGS. 1A to 1C are structural diagrams of a conventional interline-transfer CCD array.
Referring to FIG. 1A, signal charges generated in unit pixels by a light incident on each photodide 1 are simultaneously transferred to an adjacent vertical CCD channel 3. Then, the charges in the vertical CCD channel 3 are sequentially transferred downward in parallel. During this charge transfer period, the photodiodes 1 store the next charges. A horizontal CCD channel 5 is placed below the vertical CCD channel 3 for receiving the charges from the vertical CCD channel 3 to provide an output signal through an output amplifier 7.
FIGS. 1B and 1C show the position of the photodiodes and their combined output signals, respectively.
The stored charges in two adjacent photodiodes are added to each other and drawn out, where the combination of the two adjacent photodiodes is varied according to the scanning field. For example, if signals of 52+55, 58+61, etc., are provided in the first odd field, signals of 55+58, 61+64, etc., are provided in the next even field. Thus, the charge in each photodiode is provided for every field and added to the charge from the upper or the lower photodiode.
In this case, in order to enhance the horizontal resolution, more photodiodes have to be integrated, resulting in a problem that the areas of the vertical CCD channels and the photodiodes become more limited. Moreover, the driving frequency of the horizontal CCD channel is increased and thus other control and output circuits have to operate at a high speed.